The IQ2’s DDC receiver uses a 16-bit ADC that samples at 122.88Msps, and features continuous coverage from 100kHz through 55MHz. The 500mW DUC transmitter’s 14-bit DAC samples at up to 210MHz and features continuous coverage from 200kHz through 55MHz. The transmitter and receiver are completely independent which allows full duplex operation.
Transmit/receive switching is built in, as is a wide input range switch-mode power supply. Power requirements are 11VDC – 15VDC (nominally 13.8VDC) at 1A; operation below 11VDC is possible at reduced transmit power levels.
The IQ2 uses a Gigabit Ethernet port for data communications and a USB 2.0 port for firmware updates. An Altera Cyclone V® 5CEA9 FPGA with 301K LEs is used for digital processing. The 5CEA9 FPGA contains more logic elements than any other commercially produced FPGA-based SDR on the market. The size of the IQ2’s FPGA enables future implementation of dozens of virtual receivers without any hardware upgrades.
Each IQ2 transceiver is assembled and tested and loaded with the latest FPGA firmware. Included are a 12VDC power cable, an SMA to BNC Adapter Cable and an SMA to SMA cable to tie the external TX2 and HF2 antenna connectors to an internal TR switch.